About Analog Rails

We are an EDA company (Electronic Design Automation), basically electronic CAD. In our 13th year, we have created several IC design platforms that enable semiconductor design houses to automate the design of a mixed-signal systems on a chip (SOC), allowing companies to reduce design times from months to less than a day. Originally named Analog On Rails, "Rails" refers to a well structured methodology + framework. The goal was to create an automated and synchronized system that all snaps together, without the need of in-house CAD groups. Formulas, number crunching, and experts know-how and methodologies made their way into all other computer systems (accounting, mechanical engineering, digital design), and now Analog Rails is approaching completion of automating mixed signal SOC design. The analog automation and DRC/LVS correct-by-constructiontm portion was completed in 2012, and Analog Rails Basic, which is a full custom environment, and better than Virtuoso-XL, was completed in 2013, along with RCx, electromigration (EM), and non-timing digital place & route for 10,000 cells or less. Last year (2015), we added a multithreaded co-simulation simulator with the ability to simulate millions of FETs accurately, which completed the mixed signal tools suite. This allows us to sell a COMPLETE low cost IC design environment. This year (2016), our new focus is on digital place and route and adding the capability of handling 1 million logic cells, adding static timing based optimization, and releasing design management built within Analog Rails, which uses industry standard repos and SVN. Our history:

2004-2008: Completed first version of Analog Rails. Focused on flat analog block automation
importable into Virtuoso. Allowed complete proof of concept with optimization and routers.
2009: Rewrote on Open Access natively. Blocks still 100% flat. Still focused on automation.
2010: Added hierarchy, yet maintained flattened crossprobing. Improved simulation environment.
2011: Passing of electrical information back/forth to routers and editors. Finished automation.
2012: Focus on manual (full custom) editor. "Basic" created to take on "XL". Added power mesh, tightened layout.
2013: Added non timing digital place and route (< 10K logic cells), PDK GUI, DM, Graphical Pcells, RCx, EM.
2014: Started static timing based big digital optimization and automatic stdcell generation.
2015: Added a multithreaded mixed signal simulators capable of handling millions of FETS and digital behavioral.
2016: Planned completion of digital optimization. Adding robust design management that is superior to the current DM systems.

For a given topology, we expect the circuit designer to complete an amplifier, soup to nuts, in 30 minutes. The layout of a scfilter or ADC should take less than an hour. The user should: Open/create a topology, run the optimizer after providing analysis and measurement components into a testbench schematic, manual adjust the layout (or run compactor), automatically route, then run parasitic simulations. Simulations will always use the layout extracted values. There is no reason to wait 2 months to get the parasitic values incorporated into the simulation run. We believe our layout automation is so good, the circuit designers will be doing their own layouts. The designs will be better if the circuit designer does them, by tweaking the design based on black space and routing flow. Also, in the time it takes the circuit designer to explain the matching, critical paths, thermal gradients, the circuit designer can complete the layouts on their own.

Analog Rails was created by the sweat equity of developers that were mostly laid off in the Phoenix AZ area affected by the massive layoffs that occured last decade. There is no VC. The developers and their family members own over 90% of the company.

Passionate developer-owners created the code over the past 10+ years in a manner with the big picture in mind: Automation and correct by construction synchronization between tools. Our code is 100% "live" without fear of touching "as-is" code. In other words, there is no legacy code.